1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.
2. Description of the Related Art
A nonvolatile semiconductor memory device typified by an EEPROM is configured such that a tunnel insulating film, an electric charge storage layer, a top insulating film and a control gate electrode are stacked on a semiconductor substrate. Then, a high electric voltage is applied to the control gate electrode so as to infiltrate electrons into the electric charge storage layer from the semiconductor substrate through the tunnel insulating film to conduct writing operation. When the electric charge storage layer is made of a conductive material such as polycrystal silicon, the nonvolatile semiconductor memory device is called as a floating gate type semiconductor memory device. When the electric charge storage layer is made of an insulating material such as silicon nitride, the nonvolatile semiconductor memory device is called as a floating trap type semiconductor memory device.
In order to infiltrate an enough amount of electrons into the floating gate in the floating gate type semiconductor memory device, the capacitance ratio (coupling ratio) of the tunnel insulating film to the top insulating film is required to be set to an appropriate prescribed value. Conventionally, the capacitance ratio (coupling ratio) of the tunnel insulating film to the top insulating film is set to the prescribed value by enclosing the sides of the floating gate with the top insulating film.
With the development of the miniaturization of the semiconductor memory device, however, the height of the floating gate is required to be reduced. In order to realize the prescribed coupling ratio as desired while the height of the floating gate is reduced, the top insulating film is required to be thinned. However, the thinning of the top insulating film causes the increase of leak current from the floating gate and makes the storage of electric charge difficult. In this point of view, the top insulating film is made of a material with high dielectric constant so as to realize the desired coupling ratio while the thickness of the top insulating film is maintained.
Moreover, the floating trap type semiconductor memory device has the disadvantage of slow erasing operation. In order to realize fast erasing operation, it is required to discharge electrons from the electric charge storage layer into the semiconductor substrate under the condition that the infiltration of electrons from the control electrode into the electric charge storage layer is suppressed. In this point of view, the top insulating film of the semiconductor memory device is made of a material with high dielectric constant so as to realize the high insulation of the top insulating film.
In addition, in a semiconductor device such as a CMOS transistor, the gate insulating film is thinned as the semiconductor device is miniaturized, so that a large leak current via the thin gate insulating film becomes a main problem.
As the insulating film with high dielectric constant usable as the top insulating film of the semiconductor memory device and the like, the use of at least one selected from the group consisting of HfO2, HfAlO, HfSiO, HfSiON, ZrO2, ZrSiO, ZrSiON or a combination thereof is disclosed in Reference 1. Then, as the insulating material with high dielectric constant, an oxide containing La, Al and Si is disclosed in Reference 2.
[Reference 1] JP-A 2003-68897 (KOKAI)
[Reference 2] D. Mazza and S. Ronchetti, Mater Res Bull., vol. 34, No. 9, pp. 1375 to 1382, 1999
It is known that the above-described insulating film with high dielectric constant is reacted with SiO2 through thermal treatment at a temperature more than a prescribed temperature to form silicate. In the semiconductor memory device, side walls made of SiO2 are formed at both sides of the stacking structure of the tunnel insulating film, the electric charge storage layer, the top insulating film and the control gate electrode. Therefore, the top insulating film may react with the side walls through the thermal treatment for impurity activation to deteriorate the characteristics of the semiconductor memory device.
In the CMOS transistor, in contrast, since side walls made of SiN are formed at both side of the stacking structure of the gate insulating film and the gate electrode, the gate insulating film is unlikely to react with the side walls through thermal treatment even though the gate insulating film is made of the material with high dielectric constant, which is different from the semiconductor memory device. However, the gate insulating film may react with the side walls in dependence on the condition of the thermal treatment so as to deteriorate the characteristics of the CMOS transistor.
In addition, in the semiconductor device such as the CMOS transistor, if the gate insulating film is made of the insulating film with high dielectric constant, the gate insulating film may form a SiO2 layer at the surface of the silicon substrate, so that a large amount of interface states are formed to deteriorate the characteristics of the transistor.